1. Field of the Invention
The present invention relates to a semiconductor device having a nonvolatile memory and a logic circuit and, more particularly, an integrated circuit device having a double-layers gate structure and a single-layer gate structure and a method of manufacturing the same.
2. Description of the Related Art
In recent years, an integrated circuit semiconductor device has been utilized in various fields including various information devices such as a mobile device, an IC card, etc. In such semiconductor device, a nonvolatile memory such as EEPROM (Electrically Erasable Programmable ROM), etc., from/into which the user can electrically erase/program data, and a CMOS logic circuit such as ASIC (Application Specific Integrated Circuit), etc. are integrated on the same chip.
FIG. 12 is a sectional view showing a structure of a semiconductor device having the EEPROM and the CMOS logic circuit in the prior art. As shown in FIG. 12, a high voltage operating circuit (HV circuit), which is operated by a high voltage such as about 20 V necessary for erasing/programming of a memory cell, is installed in the neighborhood of the EEPROM.
As shown in FIG. 12, each memory cell of the EEPROM is composed of a memory transistor and a selector transistor connected in series with this memory transistor. The memory transistor is constructed as a double-layers gate which consists of an underlying gate oxide film 116 having a thin tunnel oxide film 118 in its partial area, a floating gate 120b, an interlayer gate oxide film 122, and a control gate 126b. 
When the voltage is applied to the control gate 126b, the tunnel current is generated via the tunnel oxide film 118 to inject/extract electrons into/from the floating gate 120b. Binary digits xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d are decided based on whether or not the storage charge exists in the floating gate 120b. Since the memory transistor is isolated from the periphery, the memory transistor can still hold the storage charge after the power supply is turned off if the charge is accumulated in the memory transistor once.
Basically the selector transistor, the transistor in the HV circuit, and the CMOS transistor in the logic circuit other than the memory transistor are formed as a single-layer gate. In many cases, in order to achieve the process matching, these transistors are formed as the double-layers gate structure to mate with the structure of the memory transistor, and a structure in which overlying and underlying gate electrodes are short-circuited partially is used.
In the double-layers gate structure, a thickness of the layer to be etched by the dry etching becomes considerably large in forming gate patterns rather than the case where the single-layer gate structure is formed. Since a time required for the etching is increased longer as the to-be-etched layer becomes thicker, the used etching mask is requested to achieve the high etching resistance. In addition, since a surface of the etching mask is also etched at the time of etching, the predetermined thickness or more is needed for the etching mask.
For example, if a resist mask is used as the etching mask, a necessary mask thickness becomes considerably large because the resist is ready to be etched. Also, since the resist is gasified during the etching process to generate new reaction adhesive, drip or deformation of the mask pattern is caused. Therefore, in forming the double-layers gate pattern, normally an inorganic film such as an SiNx film is utilized in place of the resist mask. The inorganic film mask is normally called a hard mask.
However, since a thickness of the to-be-etched layer is still considerably thick in the double-layers gate structure even if the hard mask is used, it is essentially difficult to form the fine pattern. Therefore, like the LSI for the IC card including the nonvolatile memory, if the CMOS logic circuit which is integrated together with the EEPROM on the same chip are requested to be formed as the fine patterns, as shown in FIG. 12, the double-layers gate structure is formed in the EEPROM area regardless of the burden of the process, nevertheless the single-layer gate structure is formed in the CMOS logic circuit area.
As a result, a structure which consists of the logic circuit with the single-layer gate structure and the memory cell and its peripheral circuit with the double-layers gate structure is formed on the same chip.
A method of manufacturing a LSI including the EEPROM and including the single-layer gate structure and the double-layers gate structure in the prior art will be explained with reference to FIG. 13A to FIG. 14H hereunder.
First, as shown in FIG. 13A, an n well 112 is formed in a part of the CMOS logic circuit area on a p-type semiconductor substrate 110. Then, respective circuit areas are defined by a field oxide film 114 in the LOCOS step so as to electrically isolate respective circuit areas.
Then, an n-type shallow impurity diffusion area is formed under a tunnel oxide film area of the EEPROM cell. Also, a silicon oxide film (SiO2) 116 of about 350 xc3x85 thickness is formed as a gate oxide film on a surface of the substrate. The gate oxide film 116 is removed from a tunnel oxide film forming area by the etching, and then a tunnel oxide film 118 made of a thin SiO2 film of about 90 xc3x85 thickness is formed in this area.
Then, as shown in FIG. 13B, a first polysilicon film 120 is formed. Phosphorus (P) is doped into this film to reduce the resistance value, as occasion demands. Then, a so-called ONO (oxide/nitride/oxide) film 122 serving as an interlayer gate insulating film is formed. This ONO film 122 is formed of three layers which consists of a SiO2 film obtained by thermally oxidizing a surface of the first polysilicon film 120, a SiNx film formed by the CVD method, and an SiO2 film obtained by oxidizing a surface of the SiNx film.
Then, as shown in FIG. 13C, the ONO film 122, the first polysilicon film 120, and the gate oxide film 116 formed thereunder are removed by the etching from the CMOS logic circuit area in which the single-layer gate structure is to be formed.
Then, as shown in FIG. 13D, in the CMOS logic circuit area, a thin gate oxide film 124 is formed to mate with a size of a fine transistor to be formed in this area. After this, a second polysilicon film 126 is formed on an overall surface of the substrate. Ions are implanted into a channel area in the logic circuit area to control a threshold value of the transistor, as occasion demands, and thus the impurity concentration is adjusted previously.
Then, as shown in FIG. 14E, an SiNx film 128 used as a hard mask is formed on an overall surface of the substrate. Since this SiNx film 128 is used as an etching mask in forming the double-layers gate pattern in the EEPROM area, normally such SiNx film 128 must be formed to have a large thickness of 2000 xc3x85 or more.
Then, as shown in FIG. 14F, mask patterns 128a to 128e for respective gates are formed by selectively etching the SiNx film 128. Then, the second polysilicon film 126 is etched by the RIE (Reactive Ion Etching) method using the mask patterns as the etching mask. In the EEPROM area, a surface of the interlayer gate insulating film 122 is exposed because the second polysilicon film 126 is etched. In the CMOS logic circuit area, single-layer gates 151, 152 are formed.
In this manner, the single-layer gates which are formed in the CMOS logic circuit area are patterned simultaneously by using the thick hard mask which is used to form the double-layers gates.
Then, as shown in FIG. 14G, the CMOS logic circuit area is covered with a resist film 134. In the EEPROM area and the HV circuit area, the etching of the interlayer gate insulating film 122 and the first polysilicon film 120 is continued while using the mask patterns 128a to 128c. Thus, the double-layers gates 153, 154, 155 are obtained. Then, the resist film 134 for covering the CMOS logic circuit area is removed.
Then, the ion implantation is carried out while using the gates 151 to 155, on which the hard mask is still formed, as the ion-implantation mask and then the annealing step is performed, whereby n-type impurity diffusion arcas 140a to 140g and p-type impurity diffusion areas 141a and 141b which constitute source/drain areas of respective transistors are formed.
Finally, leading electrodes 160a to 160h are formed to be extended from the interlayer insulating films 142, 144 and the source/ drain areas, and then a surface of a resultant structure is covered with a passivation film 146. As a result, a semiconductor device shown in FIG. 12 can be completed.
Since the SiNx etching mask used in patterning of the gates 151 to 155 is the insulating film, it can constitute a part of the interlayer insulating film 142. Thus, the mask is not removed and is left as it is after the steps have been finished.
As described above, in the method of manufacturing the semiconductor device having a double-layers gate structure and the single-layer gate structure in the prior art, the patterning of the double-layers gate and the single-layer gate is performed by using the hard mask which is formed by the same layer. More particularly, in the CMOS logic circuit area in which the formation of the fine pattern is demanded, the single-layer gate is formed by using as the etching mask the thick hard mask which has the etching resistance necessary for the formation of the double-layers gate.
However, the thicker the etching mask, the lower the dimensional precision of the mask pattern. Therefore, such a problem is pointed out that it is difficult to achieve the sufficient pattern precision in the logic circuit in which the formation of the fine gate pattern, e.g., the gate width of less than 0.3 xcexcm, is requested, like the LSI for the IC card including the EEPROMS.
It is an object of the present invention to form a double-layers gate and a single-layer gate with appropriate pattern precision respectively, in a semiconductor device having a nonvolatile memory with a double-layers gate structure and a logic circuit with a single-layer gate structure.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a nonvolatile memory with a double-layers gate structure and a logic circuit with a single-layer gate structure, comprising the steps of patterning a double-layers gate by using an etching mask which consists of a plurality of layered inorganic films; and patterning a single-layer gate by using an etching mask which consists of any single-layer inorganic film of the plurality of layered inorganic films,
According to this aspect, the thick etching mask consisting of a plurality of inorganic films which has the etching resistance can be used in patterning the double-layers gate. In contrast, the thin single-layer inorganic film which is suitable for the formation of the fine pattern can be used in patterning the single-layer gate.
In addition, the manufacturing method set forth in the following may be used. That is, a first gate insulating film, a first conductive film, and a second gate insulating film are layered in sequence on an overall area of a main surface of a substrate, then the first gate insulating film, the first conductive film, and the second gate insulating film in a logic circuit area are removed by etching, and then a third gate insulating film is formed on an exposed surface of the substrate in the logic circuit area. Then, a second conductive film is formed on the overall area of the main surface of the substrate, then a first inorganic film and a second inorganic film are layered on the second conductive film, and then the second inorganic film is removed in the logic circuit area by etching. After this, an etching mask for the double-layers gate is formed by etching selectively the first inorganic film and the second inorganic film in a memory cell area. In contrast, an etching mask for the single-layer gate is formed by etching selectively the first inorganic film in the logic circuit area. The single-layer gate structure is formed by etching the first conductive film in the logic circuit area by using the etching mask for the single-layer gate, whereas the double-layers gate structure is formed by etching selectively the second conductive film, the second gate insulating film, and the first conductive film in the memory cell area by using the etching mask for the double-layers gate.
According to the above manufacturing method, the layered inorganic films with the double-layers structure are formed in advance on the second conductive film formed on the substrate, then only the single-layer inorganic film is left in the logic circuit area by etching the overlying inorganic film, then the etching masks which correspond to the gate patterns are formed by etching the inorganic films in the memory cell area and the logic circuit area respectively. Therefore, in the memory cell area in which the etching resistance is required for the etching mask because the to-be-etched layer is thick, the thick inorganic films with the double-layers structure consisting of the first inorganic film and the second inorganic film can be used as the etching mask in forming the gates. On the contrary, in the logic circuit area, the single-layer thin inorganic film consisting of only the first inorganic film can be used as the etching mask, and therefore the formation of the fine pattern can be formed with high precision.
Otherwise, the manufacturing method set forth in the following may be used. That is, a first gate insulating film, a first conductive film, and a second gate insulating film are layered in sequence on an overall area of a main surface of a substrate, and then the first gate insulating film, the first conductive film, and the second gate insulating film in a logic circuit area are removed by etching. Then, a third gate insulating film is formed on an exposed surface of the substrate in the logic circuit area. Then, a second conductive film is formed on the overall area of the main surface of the substrate, and then a first inorganic film is formed on the second conductive film. After this, the first inorganic film in the logic circuit area is removed by etching, and then a second inorganic film is formed on the overall area of the main surface of the substrate. Then, an etching mask for the double-layers gate is formed by etching selectively the first inorganic film and the second inorganic film in a memory cell area. In contrast, an etching mask for the single-layer gate is formed by etching selectively the first inorganic film in the logic circuit area. The single-layer gate structure is formed by etching the first conductive film in the logic circuit area by using the etching mask for the single-layer gate, whereas the double-layers gate structure is formed by etching selectively the second conductive film, the second gate insulating film, and the first conductive film in the memory cell area by using the etching mask for the double-layers gate.
According to the above manufacturing method, the first inorganic film is formed on the second conductive film formed on the main surface of the substrate, then the first inorganic film in the logic circuit area is etched, and then the second inorganic film is formed again on the main surface of the substrate After this, the etching masks which correspond to the gate patterns arc formed by etching the inorganic films in the memory cell area and the logic circuit area respectively. Therefore, the inorganic films with the double-layers structure, which has the etching resistance, can be used as the etching mask in the memory cell area in which the double-layers gate structure is to be formed. At the same time, the thin hard mask layer with the single-layer structure, which consists of only the first inorganic film, can be used as the etching mask in the logic circuit area in which the single-layer gate structure is to be formed, and therefore the fine pattern can be formed with high precision.
According to another aspect of the present invention, there is provided a semiconductor device having a nonvolatile memory with a double-layers gate structure and a logic circuit with a single-layer gate structure, comprising a double-layers gate which is patterned by using an etching mask consisting of a first insulating inorganic film and a second insulating inorganic film; and a single-layer gate which is patterned by using an etching mask consisting of one of the first insulating inorganic film and the second insulating inorganic film; wherein the etching mask used in patterning is left on respective gates.
According to such another aspect of the present invention, the semiconductor device which has the high precision fine pattern in the logic circuit forming area can be provided since the semiconductor device can be formed by the above semiconductor device manufacturing method. In addition, the step of removing the etching mask can be omitted by leaving the used etching mask as it is, and as a result the simplification of the process can be achieved.